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library ieee;
use ieee.std_logic_1164.all;

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entity cmp_buf is
port(	D_in:	in std_logic;
	D_out:	out std_logic
);			  
end cmp_buf;

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architecture behv of cmp_buf is
begin
  process(D_in)
  begin
    D_out <= D_in;
  end process;
end behv;
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